Tkool Electronics

This, in turn, could push out the need for universal memory” technologies, such as FeRAM, MRAM, OUM and others. Universal memory” is supposed to replace flash, but the technology has not lived up to its promises, he said.

HTSW-140-17-F-D_Datasheet PDF

This, in turn, could push out the need for universal memory” technologies, such as FeRAM, MRAM, OUM and others. Universal memory” is supposed to replace flash, but the technology has not lived up to its promises, he said.

But for that to change–and Europe's network operators, at least, are desperate for it to change, if they are ever to see realistic returns on the enormous investments they made up front for their 3G licenses–the industry will need to look to other alliances to reduce chip development costs and accelerate the timetables for handset development.

By John Walko (jwalko@cmp-europe.com), London-based contributing editor to EE Times

HTSW-140-17-F-D_Datasheet PDF

Santa Cruz, Calif. — Any EDA vendor or large EDA user will tell you there's a compelling need for a standard way to express power-management intent throughout the IC design flow. The problem is that two separate groups are working toward that objective, amid profound disagreements over how to get there.

In one corner is Cadence Design Systems' Power Forward Initiative, launched in May to develop a Common Power Format (CPF) across the design flow (see May 22, page 1). At its launch, Power Forward consisted of Cadence and seven user companies–AMD, ARM, ATI Technolo- gies, Fujitsu, Freescale, NEC and TSMC. No other EDA vendors were involved, and Cadence representatives said other companies would be able to join only after the conclusion, in January 2007, of a six-month initial development effort.

At last month's Design Automation Conference, meanwhile, Texas Instruments and Nokia initiated a meeting to launch what proponents promise will be an open, inclusive and fast” low-power standards initiative. Represented at the DAC meeting were ARM, STMicroelectronics, Philips, Sun, Synopsys, Magma Design Automation, Mentor Graphics and Atrenta–as well as Cadence.

HTSW-140-17-F-D_Datasheet PDF

Just prior to DAC, Cadence had announced that other EDA vendors would be welcome to join a Power Forward advisory group, through which they would have access to the CPF 1.0 specification, expected in January, and could work with other initiative members on further standardization. But Cadence's closest competitors–Synopsys, Mentor Graphics and Magma–have thus far rejected the overture.

Things didn't get better after DAC. Jan Willis, senior vice president for industry alliances at Cadence, said her company wasn't invited to follow-up discussions for the low-power initiative that took shape at DAC. How can a group call themselves open and inclusive, and not invite Cadence?” she asked.

HTSW-140-17-F-D_Datasheet PDF

How open?Willis asserted that Power Forward also intends to be quick, open and inclusive.” While competitors such as Synopsys and Mentor Graphics have not responded to the invitation to join, she said, Power Forward is actively engaged” with numerous other companies and is getting positive feedback on its technical direction.

Power analysis tool provider Sequence Design plans to join Power Forward, said Sequence CEO Vic Kulkarni. We're looking forward to having formal meetings with Cadence to understand all the rules of engagement, and we will be pushing toward openness and neutrality,” he said.

China gains in 2004 pure-play foundry rankings

TI expands analog market lead, says analyst

Samsung gains share in flash rankings for 2004

Samsung to top Intel in capital spending for ’05

TI, Infineon leapfrog Renesas in iSuppli’s top IC rankings

访客,请您发表评论:

Powered By Tkool Electronics

Copyright Your WebSite.sitemap