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The synchronous rectifier MOSFETs were selected for optimum RDS(on) versus gate charge. The MOSFETs' turn-on is slowed by resistors R15 and R16, while its turn-off is immediate due to D3 and D4 (don't try to get by with signal diodes in this circuit). This helps the synchronous rectifiers to switch at the most optimal time. A snubber is required only on one side (C18 and R12). Pay close attention to the DC resistance (DCR) of all inductors. The one at the output, L3, exhibits a mere 4.2 milliohms, yet its DC resistance is alone responsible for a 0.4 percent power loss in the system. There are quite a few inductors capable of the current requirement that will exhibit a DC resistance of 12 to 16 milliohms. There are only two types of inductors in the entire design that carry more than a few milliamps of current. The first is the 3 microhenry unit just discussed. The second one is a 4.7 microhenry unit that always carries less than 2 amps and has a DC resistance of 9.5 milliohms. Don't throw away an entire percent or more of efficiency by not checking this parameter. The same holds true for the electrolytic capacitors. Aluminum polymer capacitors are suggested due to their extremely low equivalent series resistance (ESR).

MTSW-206-11-S-T-225-RA_Datasheet PDF

The synchronous rectifier MOSFETs were selected for optimum RDS(on) versus gate charge. The MOSFETs' turn-on is slowed by resistors R15 and R16, while its turn-off is immediate due to D3 and D4 (don't try to get by with signal diodes in this circuit). This helps the synchronous rectifiers to switch at the most optimal time. A snubber is required only on one side (C18 and R12). Pay close attention to the DC resistance (DCR) of all inductors. The one at the output, L3, exhibits a mere 4.2 milliohms, yet its DC resistance is alone responsible for a 0.4 percent power loss in the system. There are quite a few inductors capable of the current requirement that will exhibit a DC resistance of 12 to 16 milliohms. There are only two types of inductors in the entire design that carry more than a few milliamps of current. The first is the 3 microhenry unit just discussed. The second one is a 4.7 microhenry unit that always carries less than 2 amps and has a DC resistance of 9.5 milliohms. Don't throw away an entire percent or more of efficiency by not checking this parameter. The same holds true for the electrolytic capacitors. Aluminum polymer capacitors are suggested due to their extremely low equivalent series resistance (ESR).

Having an embedded processor within the FPGA will reduce the BOM and PCB layout cost. In the event that multiple processors are needed, the development tool will allow the user to create a multi-processor system to scale a system's performance or to divide software applications into simpler tasks. The Nios II core can be optimized for maximum system performance or optimized for minimum logic usage, or one that strikes a balance between the two. The core can easily be configured with features such as multipliers, user-specified cache memories, custom instructions, hardware debug logic, and more to adapt to a specific performance needs.

The Nios II Embedded Design Suite (EDS) includes support for creating customized multicore systems. Nios II processors, combined with extremely high-density FPGAs such as those in the Stratix III device family, are ideal for creating high-performance multiprocessor applications. A typical Nios II application is shown in Figure 4 .

MTSW-206-11-S-T-225-RA_Datasheet PDF

Figure 4: Typical System Application with NIOS II Embedded Processor

Embedded memories and external memory interfaces Memory is one of the key building blocks that are required for any video processing application such as video compression encoding, 2D filtering, and scaling. It is now possible to implement complete multimedia systems into a single FPGA due to the available number of internal dedicated memory blocks. These internal memory blocks include RAM, ROM, FIFO, dual port memory, and shift registers. Most systems typically require memory to support different storage requirements arising from the complexity of the functions (i.e. communications, digital signal processing, electronic data processing, and control applications).

MTSW-206-11-S-T-225-RA_Datasheet PDF

The TriMatrix memory architecture that was introduced in Stratix devices offers different memory structures that can implement a wide variety of memory functions found in complex designs. Designers can use the smaller M512 RAM blocks for first-in first-out (FIFO) functions and clock domain buffering where memory bandwidth is critical. The M-RAM block addresses the FPGA requirement for large buffering applications such as intellectual property (IP) packet buffering and system cache. The M4K blocks are ideal for medium-sized memory applications for consumer multimedia application such as digital TV video enhancement. External memory support is also available for different memory types such as DDR2 and DDR3 SDRAM and RLDRAM.

Next: High speed interfaces

MTSW-206-11-S-T-225-RA_Datasheet PDF

High speed interfaces FPGAs with built-in high-speed differential interfaces such LVDS, RSDS, mini-LVDS, and PPDS can be used for direct connection to a flat panel LCD or plasma display. A typical flat panel display will usually incorporate a programmable device together with an ASSP for video quality enhancement before delivering the image onto the display.

Figure 5 shows a complete LCD module using an FPGA for both the video processing and display panel interfacing. Besides differential interface, there are also other high-speed serial interface transceivers that are available for the high end FPGAs. For the professional video application, the serial interface can be SDI, ASI, PCI Express, or Serial Rapid IO.

A close examination of the UART specification revealed the following ambiguity: While it stated that the UART should set the interrupt signal when its buffer was empty, it was less clear on whether it should set the interrupt when the buffer was empty and the UART was subsequently programmed in interrupt mode. Basically, the question is: Should the interrupt be set when the buffer is empty or when it becomes empty? Here is a classic situation where the English language can lead to misinterpretation.

To resolve the issue, we simply corrected the UART code to generate an interrupt every time the buffer was empty. With this correction, we removed the hardware trigger and reran the emulation. The Linux boot process now ran through to completion, generating a shell in which we could start other processes and perform further tests.

It is interesting to note how far the Linux boot process was able to proceed before the error became apparent. This demonstrates the importance of a thorough and complete test of hardware and software together, prior to hardware fabrication. It turns out that Linux actually uses two UART drivers. The first, executed during the early part of the boot process, is considered a safe driver, in that it operates without using interrupts. A second driver, used for general operation, is activated after the OS kernel is initialized. It was the use of interrupts by that driver that led to the issue observed.

If we had tested the Linux process only through to initialization, it would have appeared that the UART was operating correctly, and the resulting fabricated design would have contained a bug, requiring a hardware fix. A workaround could have been inserted within the driver software, although that would have had to rely on an active polling method for UART operation rather than interrupts, thereby impairing performance.

This relatively simple example highlights the more general issue when functionality is contained in both hardware and software: The more complex the overall functional execution and degree of component interaction, the greater the opportunity for misinterpretation of fundamental operational understanding.

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