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FB-RAM does away with the capacitor used in conventional DRAM bit cells built in bulk silicon. In bulk CMOS, the charge that forms a transistor's body is tied to a fixed voltage. In SOI, the untied body is floating” in silicon above the thick oxide layer. To make the floating body behave like a capacitor, a carefully controlled voltage is applied on both sides of the body.

ER1025-84KP_Datasheet PDF

FB-RAM does away with the capacitor used in conventional DRAM bit cells built in bulk silicon. In bulk CMOS, the charge that forms a transistor's body is tied to a fixed voltage. In SOI, the untied body is floating” in silicon above the thick oxide layer. To make the floating body behave like a capacitor, a carefully controlled voltage is applied on both sides of the body.

One win is with Xyratex Ltd. (Havant, U.K.), an IBM spinout that makes hard-disk testers and storage gear. It has demonstrated a system that lets servers connect to a remote I/O box via ASI for automatic failover. The system will sample in August but won't hit volume until early 2007.

Later this year, Xyratex will evaluate plans for a follow-on product. Gary Lee, a business development manager for Xyratex, said it's a concern” that StarGen is the only silicon supplier for ASI, but added that no other switch-chip companies have products that could replace what StarGen offers.

ER1025-84KP_Datasheet PDF

Meanwhile, both IBM Corp. and graphics chip designer Nvidia Corp. recently joined the ASI SIG. IBM said it joined because some customers asked its ASIC group for ASI cores.

StarGen's Appelman is betting on 2008 as ASI's breakout year, partly because that's when the 5-Gbit/s version of Express is expected to be widely available. That version will enable common four-lane backplanes to use Express to hit their 10-Gbit-plus targets. Today's backplanes can typically only get up to about 8 Gbits with the current, 2.5-Gbit Express.

Express will also be available as a native interface on a much broader array of processors and peripheral chips by 2008. Sun, for one, will put an Express interface on Niagara2, its next-generation multicore Sparc CPU.

ER1025-84KP_Datasheet PDF

We are in a big way starting to implement PCI Express on a lot of products. It's replacing HyperTransport,” designed by Intel archrival Advanced Micro Devices, said Doug White, a technology leader in high-speed design in the router group at Cisco Systems Inc. Everyone I've talked to said Express is becoming more and more prevalent in our designs, but no one I know of is working on anything with ASI.”

Express is being used for chip-to-chip links because it is appearing on an increasing number of merchant comms chips, he added. Cisco's router group uses proprietary interfaces on its backplanes, so is not considering Express there.

ER1025-84KP_Datasheet PDF

Express ranked as the third most familiar interface and the second most likely to see increased use in an EE Times Web survey of 243 engineers conducted in the spring of 2005. At that time, 82.2 percent of respondents said they were very or somewhat familiar with Express, and 63.9 percent said they were likely to increase their use of it over two years (search www.eetimes.com for article ID: 160502125).

Express vs. RapidIOAn all-out mind-share battle is being waged in the communications sector between Express and the competing Serial RapidIO interconnect developed by Freescale Semiconductor Inc. Unlike ASI, RapidIO (RIO) is gaining traction as an interface for PowerPCs and digital signal processors, especially as a way to link the farms of DSPs found in wireless basestations.

Our COT and ASIC customers want to use this technology for their processors, graphics and high-end network ICs,” said Tsuyoshi Yamamoto, senior manager for SoC development at Fujitsu Microelectronics America. He said that customers can gain 6 percent higher frequency with 30 percent less timing optimization by using Fujitsu's statistical timing environment.

While third-party statistical timers are available, Fujitsu chose to use its own tool because commercial tools can't accurately read Anova's statistical library at this time, Yamamoto said.

ASIC and COT customers will use the statistical analysis tool for critical paths that are influenced by process variations. Fujitsu does not plan to sell the tool. Fujitsu's statistical timing environment will be available on October 2006 for the 90 and 65 nm process nodes.

Fujitsu is not exhibiting at DAC, but will discuss its statistical timing environment at panel sessions, a spokesman said.

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