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Note:What Is an Activity?

MTSW-144-07-F-D-225_Datasheet PDF

Note:What Is an Activity?

Multiple cores also provide opportunities specific to the cellular infrastructure and emerging WIMAX application domains. This is because wireless transmissions require sophisticated OFDM modems. The workload of such modems requires that multicore DSPs run faster (1 GHz compared to the 500 MHz for VoIP MP), as well as have significant hardware acceleration and coprocessors such as turbocore and Viterbi. Power constraints are also likely to reduce the number of cores per chip.

As the telecom industry enters the triple play era, it faces engineering challenges that would have been unsolvable only a few years ago. This performance bar will undoubtedly continue to raise higher, but the ability of innovative DSP chip designers to increase capacity is likely to keep pace with emerging multicore and DSP-based SoCs, continuing the ability of DSPs to meet the system performance, power, flexibility and price per channel challenges ahead.

MTSW-144-07-F-D-225_Datasheet PDF

About the author Leon Adams is the worldwide manager for DSP marketing at Texas Instruments. He is responsible for overseeing TI's DSP product roadmaps, positioning, and pricing. Adams has held a variety of engineering and management positions since joining TI in 1980. He played a key role in deriving the eXpressDSP software technology and the DSP platforms strategies for TI. Adams graduated summa cum laude with a bachelor's of science in engineering physics from Murray State University. He received a master's degree in business administration with honors from the University of Texas at Austin.

Introduction Just a couple of days ago as I pen these words, I was chatting with Bryan Hoyer from Align Engineering. After slaving away for years in their secret underground bunker, these little rapscallions have just come out of Stealth Mode”. As part of their public launch, the folks at Align have announced a patented breakthrough technology called Align Lock Loop (ALL) , which allows every LVDS input/output (I/O) pair in an FPGA to be used as a complete SERDES (Serializer/Deserializer) solution. This forms the basis for implementing fast, simple, and very affordable chip-to-chip and board-to-board communication without using large numbers of I/O pins and without involving intensive engineering that makes your eyes water.

In fact, I was so excited about the ALL concept that I decided to pen this brief technology introduction/backgrounder. Bryan promises that Align will follow this with a full-up How To” article in the not-so-distant future (after the proof-in-silicon” technology demonstration that is currently planned for sometime in Q4 2007).

MTSW-144-07-F-D-225_Datasheet PDF

Phase Lock Loops (PLLs) and Clock Data Recovery (CDR) Before we leap into the fray with gusto and abandon, it's well-worth spending a few moments reminding ourselves as to the role played by PLL and CDR functions, because these concepts will be important to our future discussions.

A PLL is a closed-loop electronic control system/function that can be used for frequency control by generating an output signal with a fixed relation to the phase of an input (reference”) signal. For the purposes of these discussions, both the input and output signals will be considered to be clock signals. The simplest form of PLL generates an output clock with the same frequency and phase as the input clock (Fig 1 ).

MTSW-144-07-F-D-225_Datasheet PDF

By means of a feedback path coupled with a phase detector, the PLL responds to both the frequency and the phase of the input signal, automatically raising or lowering the frequency of a controlled oscillator until it is synchronized to the input/reference signal in both frequency and phase.

Requirements for hypervisors From the above discussion of virtualization use cases, we can derive a number of requirements for hypervisors that can be used in a resource-constrained embedded system.

First, the hypervisor must support the processor architecture used in the embedded system. Unlike the enterprise space, where the x86 architecture is pervasive, many embedded systems use other kinds of processors. Specifically, the mobile wireless space is dominated by ARM cores; in other verticals the MIPS and Power architectures are prevalent.

The basic scenario of co-existing rich and real-time OS implies first off that the hypervisor must be real-time capable, meaning that it has bounded and short interrupt latencies.

Isolation between virtual machines is, by definition, provided by any hypervisor. However, while in enterprise systems strong isolation is the prime motivation for the use of virtualization, this is not so in embedded systems. All the various subsystems of an embedded system contribute to its overall functionality, and therefore require strong cooperation. This implies a need for low-overhead, low-latency, high-bandwidth communication channels between subsystems (i.e. virtual machines).

The hypervisor must also not consume significant resources, as this would drive up the BOM cost. Furthermore, the security use cases (PIN entry and IP protection) require that the system is highly resilient not only to software, but also hardware-based attacks. This means that all security-critical code (which includes the hypervisor) must be contained in on-chip memory. This puts very severe restrictions on the size of the hypervisor. Similar arguments can be made for the device-management use cases.

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