MTMM-144-02-T-D-012_Datasheet PDF

These potential interoperability issues are being pushed down to the chip level, with OEMs and ODMs calling on vendors to produce a single chipset that can operate in 802.11a, b, and g modes. Designers building these chips, however, face a variety of choices, depending on how one wants to optimize between performance, cost, and time-to-market. Let's examine those choices in more detail starting with the radio architecture.

Very-low IF vs. ZIF Traditionally RF receiver front-ends have been based on heterodyne/superheterodyne architectures, which use one or more intermediate frequency (IF) stages to achieve good selectivity and sensitivity properties. As a result, heterodyne/superheterodyne radios typically require a large number of discrete components, which in turn make high-level integration difficult to achieve. Driving WLAN systems to the cost structures required for mass market applications requires pushing the channel filtering function to lower frequencies through the selective use of direct-conversion— also called zero IF (ZIF)— and very low IF (VLIF) receiver architectures.

MTMM-144-02-T-D-012_Datasheet PDF

When choosing between a ZIF and VLIF architecture, it is important to carefully examine performance, compatibility with other chips in the system, and integration. In general, a designer must consider whether a ZIF radio architecture is capable of meeting the wireless data system specifications or if a VLIF architecture would better handle the performance parameters and product objectives of the application.

A major advantage of ZIF is cost. ZIF architectures have proven to be a good alternative for lowering discrete filtering requirements, decreasing circuit-board areas, reducing component counts and power consumption, and providing a roadmap to ongoing cost reductions over time. ZIF eliminates the need for expensive RF image-rejection filters and IF channel-selection filters while offering the potential for a high degree of integration.

ZIF is a proven architecture for CCK modulation-based 802.11b designs. The complete elimination of an IF stage implies some important performance characteristics that are unique to direct conversion receivers, such as sensitivity and linearity. Since direct conversion translates the radio signal directly to baseband, the majority of the gain and filtering are performed in a frequency band from DC to the signal bandwidth.

MTMM-144-02-T-D-012_Datasheet PDF

There are, however, some issues with the ZIF architecture. Since the local oscillator is so close to the input frequency, the signal can fold around the DC components of the input signal. In the process, intrinsic DC offsets in the signal path can be unintentionally amplified and, in turn, degrade the dynamic range available in the circuit. Additionally, DC offsets can be created if some of the on-channel local oscillator (LO) signal leaks to the RF front-end and is then down-converted (Figure 1) .

MTMM-144-02-T-D-012_Datasheet PDF

When employing a ZIF architecture, designers must take measures to ensure that the folded and non-folded frequency components do not overlap in order to prevent signal corruption. Precision analog design techniques can minimize circuit DC offsets, and provide a basis for adjusting most of the remaining offset using calibration methods.

VLIF architectures have many of the desirable properties of ZIF architectures, but without the DC offset problems. This is of particular benefit in OFDM-based systems like 802.11a and g.

Tiling of lower level blocks achieves better performance and cost than arrays, and can be programmed based on performance-level abstraction reliably. However, they cover a very narrow range due to the fixed nature of the analog sub blocks, and offer little flexibility. .They are best suited to platforms where very little value comes from the ability to change the analog block. This approach is best suited to metal-only programmable solutions such as FPGAs.

Hard analog IP blocks are another alternative. Hard IP does enable abstracted levels of design due to availability of higher-level models, and can sometimes be made configurable such as through programmable bits in a PLL. Programmable PLLs can be used within an analog block with elements such as converters to enable a level of flexibility. The trade-off is that there is usually an area penalty to using such a block and this directs results in cost inefficiencies that make this a non-viable solution for platforms since platforms are best suited for high volume cost-sensitive end-user applications. This approach can be applied to a variety of platform types.

Fast and reliable

Geometric programming-based (GP-based) analog components rely on the coding of circuit and process characteristics into a geometric program. Then a solver is used to synthesize the physical circuit that will achieve the users system performance specifications. This approach is functionally limited to whatever circuit/process combination has been coded, but offers a reliable system programming level of abstraction, and very fast (hours) implementation times. It also readily enables system performance tradeoffs and is broadly applicable to a variety of platform types.

Thus, while there is a range of options for configurable analog IP, it is clear that GP-based synthesizable analog IP offers significant advantages for frequently used functions. As a focus of application platforms is on very specific types of systems, where the same types of functions are likely to be used repeatedly, there is a very good fit.


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