The following article was provided by Bill Ong, a senior research analyst at American Technology Research Inc. in San Francisco. American Technology Research is an independent research house based in Old Greenwich, Conn.

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The following article was provided by Bill Ong, a senior research analyst at American Technology Research Inc. in San Francisco. American Technology Research is an independent research house based in Old Greenwich, Conn.

MTSW-145-08-F-D-280_Datasheet PDF

The following article was provided by Bill Ong, a senior research analyst at American Technology Research Inc. in San Francisco. American Technology Research is an independent research house based in Old Greenwich, Conn.

Dynamic verification flow

Fully exploiting the benefits of design and verification on multiple levels of abstraction, the flexibility and scalability (through, for example, compute farms) of a software-based simulation flow, and the debugging capabilities it can provide, requires the simulation capability to be mainly software based. Existing verification flows focus on the effective creation of testbenches, random stimulus generation, coverage metrics, and core RTL simulation technology. DFV requires these flows to be extended to include assertions and multi-level interface design.

MTSW-145-08-F-D-280_Datasheet PDF

Full-chip simulations ” even if part of the chip is simulated at the transaction level ” can have hundreds, if not thousands of embedded assertions. This requires that access to the design objects is direct and does not incur any overhead. The only way to achieve this is to have assertion execution directly incorporated in the simulation kernel.

An added benefit is that this enables an integrated debugging environment, so that designers face only a single environment to debug and analyze both the design and the assertions. Similarly, the capability to gather both code coverage and assertion/functional coverage metrics, which is a required element of any verification methodology, needs to be supported with very low overhead to not slow down the simulation.

The second key technology of the DFV methodology, multi-level interface design, needs to be directly supported by system-level tools and simulators. From a simulation perspective the main requirement relates to debugging. Transactions need to be visualized and shown in the same environment as the RTL and the assertions, so that a designer, debugging a problem, can analyze them concurrently.

MTSW-145-08-F-D-280_Datasheet PDF

Some design/verification teams incorporate hardware-based acceleration or rapid prototyping in their flows. Typically, these techniques can only be used late in a typical project timeline because all the RTL has to be available in a synthesizable form. The DFV methodology accommodates these hardware-assisted flows by requiring assertions to be synthesizable.

Interface constraints, assumptions and design properties, can be leveraged in, for example, an FPGA-based prototyping flow. Simply including the assertions about the design and synthesizing them onto the FPGA fabric (at the cost of extra real estate) improves designers visibility into the design and gives them the ability to monitor results and be notified when they are violated, thereby substantially aiding the designer in finding the remaining bugs in the design when the design is placed into a (near) at-speed operating environment.

MTSW-145-08-F-D-280_Datasheet PDF

Finally, a very important aspect of simulation is the API into the simulator, especially the requirement of including C/C++/SystemC functionality into the (transaction-level) design. Another requirement is a low overhead, fast, standard interface covering the multiple levels of abstraction.

Formal-analysis flow

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