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A pulse coder modulation (PCM) interface with transmit and receive FIFOs is also required to enable the designer to seamlessly connect a variety of audio codecs as well as audio codec/SLIC combo devices for VoIP adapters.

RS73F1JTTD1180B_Datasheet PDF

A pulse coder modulation (PCM) interface with transmit and receive FIFOs is also required to enable the designer to seamlessly connect a variety of audio codecs as well as audio codec/SLIC combo devices for VoIP adapters.

The telecommunications infrastructure market has undergone a tumultuous transformation over the past several years. In the wake of the overinvestment that characterized the late 1990s, the industry has seen little investment in new technology since its peak at the turn of the century. But today, the market is showing signs of revival.

RS73F1JTTD1180B_Datasheet PDF

Led by major service providers, the industry is entering a new technology transition as it migrates from circuit-switched to packet-based networks. Sprint, for example, recently announced plans to move up to half of its 8 million local lines to packet-based networks over the next six years, with the goal of moving all lines within the next 11 years. Competitors like AT&T and Verizon are making similar decisions as they look for ways to generate additional revenue by bundling voice and data services. In fact, while analysts at Pyramid Research forecast wireline capex to grow at an average of 3 percent over the next several years, spending on Internet Protocol-based equipment is expected to grow at four times that rate.

However, this is hardly the same industry it was just a few years ago. To survive the recent downturn, most telecommunications OEMs dramatically reduced staffing levels. As of last year the top nine public OEMs in the industry had reduced their head count by more than 50 percent from their peak in 2000. Nor did research and development escape the cuts. Today those same nine OEMs employ 47 percent fewer R&D engineers than they did just three years ago. More often than not, the group within R&D taking the greatest hit was ASIC design.

Where once developers used custom ASICs to build in product differentiation, today they are turning to off-the-shelf alternatives such as high-performance network processors to extend performance more cost-effectively. At the same time, growing support for industry-standard interfaces such as SPI-3 and SPI-4, and backplane fabrics such as PCI Express, Advanced Switching and Gigabit Ethernet, are helping reduce the need for proprietary solutions. This evolution allows OEMs to focus their critical resources on true differentiation rather than reinventing the wheel.

RS73F1JTTD1180B_Datasheet PDF

To succeed in this new environment of developing state-of-the-art infrastructure products with fewer engineering resources, OEMs should look to build close development relationships with their critical IC suppliers. Equipment makers will need suppliers that are intimately familiar with their application requirements and capable of consolidating costs by replacing what were once custom functions with off-the-shelf solutions.

By leveraging decades of expertise in the development of high-performance network silicon, by extending their system knowledge through new partnerships and acquisitions, and by staying at the forefront of technology by designing industry-leading semiconductor solutions, IC suppliers can offer OEMs the partner they need to develop high-speed packet-processing products for next-generation advanced network services.

RS73F1JTTD1180B_Datasheet PDF

Greg Lang, President and Chief Executive Officer, Integrated Device Technology Inc., Santa Clara, Calif.

Processor power consumption is a hot topic today (no pun intended). Consumers' appetites for sophisticated portable electronic devices are strong. But consumers want it all: they want feature-packed devices in small, slim hand-held form factors with good battery life. To meet these expectations, system designers must give high priority to minimizing power consumption.

Other standby power concerns are not so easily dealt with. For instance, to achieve high density, memory-based FPGAs use 90-nm process technology. This process has a greater transistor leakage than prior technologies, drawing current even when the circuits are not clocking. Both the logic and the interconnect memory of these FPGAs suffer from the increased leakage, raising the device's standby current.

Technology choice controls this concern. The small footprint of the antifuse allows these FPGAs to achieve high density without needing 90-nm technology, so they can use a process that has less leakage. They also need less standby current in general because they do not need active transistors to maintain device configuration; programming the antifuse causes a physical change that needs no power to maintain. Some antifuse devices can offer standby currents as low as 17 microamps.

While standby current is important for battery-powered designs, operating current affects all designs. Fortunately, designers can take steps to reduce a design's average operating current regardless of process technology. FPGA product lines have evolved, improving their architectures to give designers some tools for reducing average power. One major improvement has been to change the internal clocking structure.

Quadrant clocking Instead of a single clocking tree that covers the chip, some FPGAs now use quadrant-based clocking, a clock distribution structure that gives independent clocks to FPGA segments. It allows designs to be partitioned using gated clocks, so that a segment can be put into a slow clock or a suspended state to save power when its function is not active. The ability to stop clocking unused segments is especially valuable in designs where only a portion of the system must be continually active and the rest used only on demand. For example, a device can halt its processor until a key press or other I/O event signals the need for it to perform some function.

For systems where the triggering results from a human action, the power savings can be tremendous. Human interaction intervals are no faster than milliseconds, whereas the device can complete its task in microseconds. Most of the system's time, therefore, is spent waiting for a human action. Gated clocks allow suspension of all functions but the human interfaces during that wait time, saving considerable power.

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