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SynTest (San Jose, Calif.) said the patented invention is generally referred to as staggered skewed-load” or staggered launch-on-shift” and is a method for providing true at-speed testing for synchronous and asynchronous multi-clock, multi-frequency domains. The method provides ordered capture clocks to detect or locate faults within multiple clock domains and faults crossing clock domains in an integrated circuit during at-speed BIST or at-speed scan-testing, according to Syntest.

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